The present invention relates to a ferroelectric memory in which a plurality of memory cells each having a transistor and a ferroelectric capacitor are arranged in a matrix.
FIG. 25 shows a circuit configuration of a ferroelectric memory common to first and second conventional examples and embodiments of the present invention. As shown in FIG. 25, a ferroelectric memory cell is of a one-transistor one-capacitor type having one transistor and one ferroelectric capacitor. A gate electrode of the transistor of the ferroelectric memory cell is connected to a word line and a drain electrode of the transistor is connected to a bit line. One electrode of the capacitor of the ferroelectric memory cell is connected to a plate line and the other electrode of the capacitor is connected to a source electrode of the transistor. Thus, the ferroelectric memory cell is controlled by signals applied to the plate line, the word line and the bit line.